Electronic communication products such as those for wireless LAN (local area network), UWB (ultra wideband), mobile communication, entertainment, etc. require high communication qualities, high data transmission rates and diversified bands within each frequency range. As a transceiver commonly used in a communication system, the quality of RF (radio frequency) signals generated by a clock generator thereof is critical to its performance. Clock generators typically used in the RF field include self-excited variable-frequency oscillators, crystal oscillators and frequency synthesizers. A large tuning range is essential to the above-mentioned requirements for various applications.
A PLL (phase locked loop) circuit is commonly used in a frequency synthesizer of an electronic communication system to eliminate at least the frequency and phase shifts between a transmitting end and a receiving end caused by environmental factors. FIG. 1 schematically illustrates a typical PLL circuit 101, including a phase/frequency detector (PFD) 1010, a charge pump 1011, a loop filter 1012 and a voltage controlled oscillator (VCO) 1013. When the PLL circuit 101 performs phase lock according to a reference clock signal, the VCO 1013 outputs a feedback clock signal to the PFD 1010 while the PFD 1010 outputs an up/down counting signal according to a phase/frequency difference between the reference clock signal and the feedback clock signal. The up/down counting signal is then converted into a control voltage by the charge pump 1011 and the loop filter 1012 to be outputted to the VCO 1013, thereby locking the phase/frequency of the feedback clock signal with those of the reference clock signal.
As known to those skilled in the art, in an electronic communication system, a frequency synthesizer can be used to modulate a data signal that is afterwards demodulated to recover the data signal. Conventionally, a single VCO is used in the PLL circuit to obtain the feedback clock signal. However, for an electronic device requiring a large tuning range, multiple VCOs are utilized to output the feedback clock signal with different frequencies with a large tuning range.
Please refer to FIG. 2A showing a PLL circuit 201 with multiple VCOs, including a phase/frequency detector (PFD) 2010, a charge pump 2011, a loop filter 2012 and a plurality of voltage controlled oscillators (VCOs) 2013˜2018. The VCOs 2013˜2018 can be switched ON/OFF by enabling signals (not shown). Furthermore, each of the VCOs 2013˜2018 covers a predetermined frequency range so that the VCOs 2013˜2018 cover a large frequency range. For example, the VCO 2013 covers a frequency range of 950˜1150 MHz; the VCO 2014 covers a frequency range of 1150˜1350 MHz; the VCO 2015 covers a frequency range of 1350˜1550 MHz; the VCO 2016 covers a frequency range of 1550˜1750 MHz; the VCO 2017 covers a frequency range of 1750˜1950 MHz; and the VCO 2018 covers a frequency range of 1950˜2150 MHz. Therefore, the VCOs 2013˜2018 can cover a large frequency range of 950˜2150 MHz. FIG. 2B shows the frequency range of VCOs 2013˜2018 covering 9 bands.
As the operating frequency of a VCO is not stable, calibration is required after the circuit is powered on to find the optimal point in a band, e.g. the center of each band. It is thus important to calibrate VCOs efficiently.